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P4C1048L LOW POWER 512K x 8 CMOS STATIC RAM
FEATURES
VCC Current -- Operating: 35mA -- CMOS Standby: 100A Access Times --45/55/70/100 ns Single 5 Volts 10% Power Supply Easy Memory Expansion Using CE and OE Inputs Common Data I/O Three-State Outputs Fully TTL Compatible Inputs and Outputs Advanced CMOS Technology Automatic Power Down Packages --32-Pin 600 mil Plastic and Ceramic DIP --32-Pin 445 mil SOP --32-Pin TSOP II
DESCRIPTION
The P4C1048L is a 4 Megabit low power CMOS static RAM organized as 512K x 8. The CMOS memory requires no clocks or refreshing, and has equal access and cycle times. Inputs are fully TTL-compatible. The RAM operates from a single 5V10% tolerance power supply. Access times as fast as 45 ns are availale. CMOS is utilized to reduce power consumption to a low level. The P4C1048L device provides asynchronous operation with matching access and cycle times. Memory locations are specified on address pins A0 to A18. Reading is accomplished by device selection (CE low) and output enabling (OE) while write enable (WE) remains HIGH. By presenting the address under these conditions, the data in the addressed memory location is presented on the data input/output pins. The input/output pins stay in the HIGH Z state when either CE is HIGH or WE is LOW. The P4C1048L is packaged in a 32-pin 445 mil plastic SOP, 32-pin TSOP II, or 600 mil plastic or ceramic sidebrazed DIP.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATION
DIP (P600, C10), SOP (S12), TSOP II (T4) TOP VIEW
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P4C1048L
RECOMMENDED OPERATING TEMPERATURE & SUPPLY VOLTAGE
Temperature Range (Ambient) Commercial (0C to 70C) Industrial (-40C to 85C) Military (-55C to 125C) Supply Voltage 4.5V VCC 5.5V 4.5V VCC 5.5V 4.5V VCC 5.5V
MAXIMUM RATINGS(a)
Stresses greater than those listed can cause permanent damage to the device. These are absolute stress ratings only. Functional operation of the device is not implied at these or any other conditions in excess of those given in the operational sections of this data sheet. Exposure to Maximum Ratings for extended periods can adversely affect device reliability. Symbol VCC VTERM TA STG IOUT ILAT Parameter Supply Voltage with Respect to GND Terminal Voltage with Respect to GND (up to 7.0V) Operating Ambient Temperature Storage Temperature Output Current into Low Outputs Latch-up Current >200 Min -0.5 -0.5 -55 -65 Max 7.0 VCC + 0.5 125 150 25 Unit V V C C mA mA
CAPACITANCES(d)
(VCC = 5.0V, TA = 25C, f = 1.0 MHz) Symbol CIN COUT Parameter Input Capacitance Output Capacitance Test Conditions VIN = 0V VOUT = 0V Max 6 8 Unit pF pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol Parameter Temperature Range Commercial ICC Dynamic Operating Current Industrial Military * -45 20 25 35 -55 20 25 35 -70 20 25 35 -100 20 25 35 mA Unit
*Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously enabled for writing, i.e. CE and WE VIL (max), OE is high. Switching inputs are 0V and 3V.
Notes: a. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to MAXIMUM rating conditions for extended periods may affect reliability. b. Extended temperature operation guaranteed with 400 linear feet per minute of air flow. c. Transient inputs with VIL and IIL not more negative than -3.0V and -100mA, respectively, are permissible for pulse widths up to 20 ns. d. This parameter is sampled and not 100% tested.
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P4C1048L
DC ELECTRICAL CHARACTERISTICS
(Over Recommended Operating Temperature & Supply Voltage)(b) Symbol VIH VIL VHC VLC VOL VOH Parameter Input High Voltage Input Low Voltage CMOS Input High Voltage CMOS Input Low Voltage Output Low Voltage (TTL Load) Output High Voltage (TTL Load) Input Leakage Current IOL = +2.1 mA, VCC = Min. IOH = -1 mA, VCC = Min. VCC = Max. VIN = GND to VCC VCC = Max., ILO Output Leakage Current CE = VIH, VOUT = GND to VCC ISB CE VIH Standby Power Supply Current (TTL Input Levels) VCC= Max, f = Max., Outputs Open Standby Power Supply Current (CMOS Input Levels) CE VHC VCC= Max, f = 0, Outputs Open VIN VLC or VIN VHC
N/A = Not Applicable
Test Conditions
P4C1048L Unit Min Max VCC +0.5 V 2.2 0.8 -0.5(c) VCC -0.2 VCC +0.5 -0.5(c) 0.2 0.4 2.4 Mil. Ind./Com'l. Mil. Ind./Com'l. -10 -5 -10 -5 +10 +5 +10 +5 A V V V V V A
ILI
Mil. Ind./Com'l.
___ ___
5 3
mA
Mil. Ind./Com'l.
___ ___
100 30
A
ISB1
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P4C1048L
AC ELECTRICAL CHARACTERISTICS - READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage) Symbol tRC tAA tAC tOH tLZ tHZ tOE tOLZ tOHZ tPU tPD Parameter Read Cycle Time Address Access Time Chip Enable Access Time Output Hold from Address Change Chip Enable to Output in Low Z Chip Disable to Output in High Z Output Enable Low to Data Valid Output Enable Low to Low Z Output Enable High to High Z Chip Enable to Power Up Time Chip Disable to Power Down Time 0 45 5 18 0 55 5 10 18 22 5 20 0 70 Min 45 45 45 5 10 20 25 5 25 0 100 -45 Max Min 55 55 55 5 10 25 35 5 35 -55 Max Min 70 70 70 5 10 35 45 -70 Max -100 Min Max 100 100 100 Unit ns ns ns ns ns ns ns ns ns ns ns
READ CYCLE NO. 1 (OE CONTROLLED)(1) OE
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P4C1048L
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
READ CYCLE NO. 3 (CE CONTROLLED) CE
Notes: 1. WE is HIGH for READ cycle. 2. CE and OE are LOW for READ cycle. 3. ADDRESS must be valid prior to, or coincident with later of CE transition LOW.
4. Transition is measured 200 mV from steady state voltage prior to change, with loading as specified in Figure 1. This parameter is sampled and not 100% tested. 5. READ Cycle Time is measured from the last valid address to the first transitioning address.
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P4C1048L
AC CHARACTERISTICS - WRITE CYCLE
(Over Recommended Operating Temperature & Supply Voltage) Symbol tWC tCW tAW tAS tWP tAH tDW tDH tWZ tOW Parameter Write Cycle Time Chip Enable Time to End of Write Address Valid to End of Write Address Set-up Time Write Pulse Width Address Hold Time Data Valid to End of Write Data Hold Time Write Enable to Output in High Z Output Active from End of Write 5 -45 Min Max 45 35 35 0 35 0 25 0 18 5 -55 Min Max 55 40 40 0 40 0 30 0 20 5 -70 Min 70 60 60 0 50 0 35 0 25 5 Max -100 Min Max 100 75 75 0 60 0 45 0 35 Unit ns ns ns ns ns ns ns ns ns ns
WRITE CYCLE NO. 1 (WE CONTROLLED)(6,7) WE
Notes: 6. CE and WE are LOW for WRITE cycle. 7. OE is LOW for this WRITE cycle to show tWZ and tOW. 8. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high impedance state. 9. Write Cycle Time is measured from the last valid address to the first transitioning address.
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P4C1048L
TIMING WAVEFORM OF WRITE CYCLE NO.2 (CE CONTROLLED)(6) CE
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input Timing Reference Level Output Timing Reference Level Output Load GND to 3.0V 3ns 1.5V 1.5V See Fig. 1 and 2
TRUTH TABLE
Mode Standby DOUT Disabled Read Write CE OE WE H L L L X H L X X H H L I/O High Z High Z DOUT DIN Power Standby Active Active Active
Figure 1. Output Load
* including scope and test fixture.
Figure 2. Thevenin Equivalent
Note: Because of the high speed of the P4C1048L, care must be taken when testing this device; an inadequate setup can cause a normal functioning part to be rejected as faulty. Long high-inductance leads that cause supply bounce must be avoided by bringing the VCC and ground planes directly up to the contactor fingers. A 0.01 F high frequency capacitor is also required between VCC and ground.
To avoid signal reflections, proper termination must be used; for example, a 50 test environment should be terminated into a 50 load with 1.77V (Thevenin Voltage) at the comparator input, and a 589 resistor must be used in series with DOUT to match 639 (Thevenin Resistance).
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P4C1048L
DATA RETENTION
Symbol VDR Parameter VCC for Data Retention Test Conditions CE VCC -0.2V, VIN VCC -0.2V or VIN 0.2V VDR = 2.0V ICCDR Data Retention Current VDR = 3.0V tCDR tR Chip Deselect to Data Retention Time Operating Recovery Time Comm/Ind Military Comm/Ind Military 0 tRC Min 2.0 Max 5.5 20 200 30 300 ns ns Unit V A A
See Retention Waveform
1. CE1 VDR -0.2V, CE2 VDR -0.2V or CE2 0.2V; or CE1 0.2V, CE2 - 0.2V; VIN VDR -0.2V or VIN 0.2V
LOW VCC DATA RETENTION WAVEFORM
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P4C1048L
ORDERING INFORMATION
SELECTION GUIDE
The P4C1048L is available in the following temperature, speed and package options.
Temperature Range Commercial Speed (ns) Package Plastic DIP (600 mil) Side Brazed DIP (600 mil) Plastic SOP (445 mil) TSOP II Industrial Plastic DIP (600 mil) Side Brazed DIP (600 mil) Plastic SOP (445 mil) TSOP II Military Military Processed* Side Brazed DIP (600 mil) Side Brazed DIP (600 mil) 45 -45PC -45CWC -45SC -45TC -45PI -45CWI -45SI -45TI N/A N/A 55 -55PC -55CWC -55SC -55TC -55PI -55CWI -55SI -55TI N/A N/A 70 -70PC -70CWC -70SC -70TC -70PI -70CWI -70SI -70TI -70CWM -70CWMB 100 -100PC -100CWC -100SC -100TC -100PI -100CWI -100SI -100TI -100CWM -100CWMB
* Military temperature range with MIL-STD-883 Class B processing.
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P4C1048L
Pkg # # Pins Symbol A b b2 C D E eA e L Q S1 S2
C10
32 (600 mil) Min Max 0.225 0.014 0.026 0.045 0.065 0.008 0.018 1.680 0.510 0.620 0.600 BSC 0.100 BSC 0.125 0.200 0.015 0.070 0.005 0.005 -
SIDEBRAZED DUAL IN-LINE PACKAGE
Pkg # # Pins Symbol A A1 A2 B C D e E H L L1
S12
32 (445 Mil) Min Max 0.118 0.004 0.101 0.111 0.014 0.020 0.006 0.012 0.793 0.817 0.050 BSC 0.440 0.450 0.546 0.566 0.023 0.039 0.047 0.063 0 4
SOIC/SOP SMALL OUTLINE IC PACKAGES
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P4C1048L
Pkg # # Pins Symbol A A1 b b2 C D E1 E e eB L
P600
32 (600 mil) Min Max 0.160 0.200 0.015 0.014 0.023 0.045 0.070 0.006 0.014 1.600 1.700 0.526 0.548 0.590 0.610 0.100 BSC 0.600 BSC 0.120 0.150 0 15
PLASTIC DUAL IN-LINE PACKAGE
Pkg # # Pins Symbol A A2 b D E e HD
T4
32 Min Max 0.037 0.041 0.047 0.012 0.020 0.395 0.405 0.820 0.831 0.050 BSC 0.455 0.471
TSOP II PACKAGE
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P4C1048L
REVISIONS
DOCUMENT NUMBER: DOCUMENT TITLE: REV. OR A B C D ISSUE DATE Oct-05 Nov-06 Dec-06 May-07 Jul-07 SRAM129
P4C1048L LOW POWER 512K x 8 CMOS STATIC RAM
ORIG. OF CHANGE JDB JDB JDB JDB JDB
DESCRIPTION OF CHANGE New Data Sheet Minor corrections to DC Electrical Characteristics and Data Retention tables Update SOIC/SOP package drawing. Added 45/55 ns and PDIP Corrected error in selection guide; added TSOP II package
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